The Internet of Things (IoT) ecosystem and the rapid advancement of consumer devices necessitate solutions that provide both computer efficiency and hardware-level security. Compute-in-memory (CIM) is developing as an effective edge computing approach in IoT systems because it reduces data transit between memory and processors. In this work, a 10T static random access memory (SRAM)-based multi-stage bidirectional ring oscillator (MBRO) physical unclonable function (PUF) is designed using a CIM approach to reduce latency and generate double challenge response pairs (CRPs) that improve hardware security. Reconfigurable SRAM cells with tristate inverters allow bidirectional control, and the integration of transmission gates enables the configuration of multistage ring oscillators (ROs), proving the potential of the SRAM array for diverse operations. The proposed architecture not only ensures reliable functioning but also allows flexible activation and deactivation of the oscillator and inverter, lowering power consumption during idle periods and improving the stability of oscillation patterns with frequencies of 1.53 GHz, 942.9 MHz, and 652.5 MHz, respectively, for three-, five-, and seven-stage MBRO PUF. The area utilized by the seven-stage MBRO is 11.43 μm2 with low power consumption of 32 μW . The selection of MBRO PUF based on the number of stages according to the application affirms that the proposed MBRO PUFs are highly efficient designs with strong uniqueness and reliability. Its uniqueness is 49.6%, 49.4%, and 48% for three, five, and seven stages. By balancing security and power efficiency requirements, it makes it suitable for integration into resource-constrained environment and embedded systems.